SAT Visualization Examples

Pictures on this page were generated with the help of yEd from yWorks.
See this paper for background information about the graphs.
Shown images were partially generated at a non-zero search depth of the DP algorithm.

Click on images for high resolution versions of the pictures.

Picture 1: Software-Verification (alloy-sectors5)

(Picture 1: alloy_sectors5)

Picture 2: Hardware-Verification (bmc-ibm-2-root-part)

(Picture 2: bmc-ibm-2-root-part) (Picture 2: bmc-ibm-2-root-part-layout2)

Picture 3: Hardware-Verification (bmc-ibm-2-root)

(Picture 3: bmc-ibm-2-root)

Picture 4: Product Configuration (C202-FW-1)

(Picture 4: C202-FW-1)

Picture 5: DIMACS Benchmark (hanoi4)

(Picture 5: hanoi4)

Pictures 6 and 6a: DIMACS Benchmarks (hole10/hole6)

(Picture 6: hole10) (Picture 6: hole6)
(hole10.eps) (hole6.eps)

Picture 7: DIMACS Benchmark (ssa0432-003)

(Picture 7: ssa0432-003) (Picture 7: ssa0432-003-layout2)

Picture 8: DIMACS Benchmark (ssa2670-130)

(Picture 8: ssa2670-130)

Carsten Sinz
Last modified: Mon May 3 11:42:36 MEST 2004